View SAF-XC822-1FRI_1374032.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet v1.1 2010-10 microcontrollers xc822/824 8-bit single-chip microcontroller
edition 2010-10 published by infineon technologies ag 81726 munich, germany ? 2010 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infin eon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warr anties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet v1.1 2010-10 microcontrollers xc822/824 8-bit single-chip microcontroller
xc822/824 data sheet v1.1, 2010-10 xc822/824 data sheet revision history: v1.1 2010-10 previous versions: v1.0 page subjects (major change s since last revision) page 3 automotive variants were added in table 2. we listen to your comments is there any informati on in this document that you feel is wrong, uncle ar or missing? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to th is document) to: mcdocu.comments@infineon.com
xc822/824 table of contents data sheet 1 v1.1, 2010-10 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 pin definitions and func tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 jtag id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7 chip identification num ber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.1 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.2 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1.3 operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.1 input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.2 supply threshold characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2.3 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.3.1 adc conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.3.2 out of range comparator characteristic s . . . . . . . . . . . . . . . . . . . . . 29 3.2.4 flash memory parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.5 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3.2 output rise/fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3.3 oscillator timing and wake-up timing . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.4 on-chip oscillator characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3.5 ssc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.5.1 ssc master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.5.2 ssc slave mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.3.6 spd timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4 package and qua lity declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 quality declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table of contents
xc822/824 table of contents data sheet 2 v1.1, 2010-10
xc822/824 summary of features data sheet 1 v1.1, 2010-10 1 summary of features the xc822/824 has the following features: ? high-performance xc800 core ? compatible with sta ndard 8051 processor ? two clocks per machine cycl e architecture (for memory access without wait state) ? two data pointers ? on-chip memory ? 8 kbytes of boot rom, li brary rom and user routines ? 256 bytes of ram ? 256 bytes of xram ? 2/4 kbytes of flash (includes memory protection strategy) ? i/o port supply at 2.5 v - 5.5 v and core logic supply at 2.5 v (generated by embedded voltage regulator) figure 1 xc822/824 functional units ? power-on reset generation ? brownout detection for io s upply and core logic supply ? 48 mhz on-chip osc for clock generation ? loss-of-clock detection (more features on next page) port 0 port 1 port 2 xc800 core uart adc 10-bit 4-channel boot rom 8k bytes xram 256 bytes ram 256 bytes on-chip debug support timer 0 16-bit timer 1 16-bit timer 2 16-bit watchdog timer ssc 2/4k bytes flash capture/compare unit 16-bit compare unit 16-bit 7-bit digital i/o 6-bit digital i/o 4-bit digital/ analog input iic mdu led and touch sense controller real-time clock
xc822/824 summary of features data sheet 2 v1.1, 2010-10 features: (continued) ? power saving modes ? idle mode ? power-down mode with wake-up capability via re al-time clock interrupt ? clock gating control to each peripheral ? programmable 16-bit watchd og timer (wdt) running on independent oscillator with programmable window feature for refresh operation and warning prior to overflow ? three ports ? up to 17 pins as digital i/o ? 4 pin as digi tal/analog input ? 4-channel, 10-bit adc ? support up to 3 di fferential input channel ? results filtering by data re duction or digital low-pass filt er, for up to 13-bit results ? up to 4 channels, ou t of range comparator ? three 16-bit timers ? timer 0 and time r 1 (t0 and t1) ? timer 2 (t2) ? periodic wake-up timer ? multiplication/division unit for arithmetic operations (mdu) ? capture and compare unit fo r pwm signal generation (ccu6) ? a full-duplex or half-dupl ex serial interface (uart) ? synchronous serial channel (ssc) ? inter-ic (iic) serial interface ? led and touch-sense controller (ledtscu) ? on-chip debug support via single pin dap interface (spd) ? packages: ? pg-dso-20 ? pg-tssop-16 ? temperature range t a : ? saf (-40 to 85 c) ? sax (-40 to 105 c) ? sak (-40 to 125 c)
xc822/824 summary of features data sheet 3 v1.1, 2010-10 xc822/824 variant devices the xc822/824 product family features devices with di fferent configurations, program memory sizes, packages op tions and temperature profil es, to offer cost-effective solutions for different ap plication requirements. the list of xc822/824 device configurations are summarized in table 1 . the type of packages available ar e tssop-16 for xc822 and dso-20 for xc824. table 2 shows the device sales type av ailable, based on above device. table 1 device configuration device name mdu module ledtscu module xc822/824 no no xc822/824m yes no xc822/824t no yes xc822/824mt yes yes table 2 device profile sales type device type program memory (kbytes) temp- erature profile ( c) package type quality profile saf-xc822t-0fri flash 2 -40 to 85 pg-tssop-16 industrial SAF-XC822-1FRI flash 4 -40 to 85 pg-tssop-16 industrial saf-xc822t-1fri flash 4 -40 to 85 pg-tssop-16 industrial saf-xc822m-1fri flash 4 -40 to 85 pg-tssop-16 industrial saf-xc822mt-1fri flash 4 -40 to 85 pg-tssop-16 industrial saf-xc824m-1fgi flash 4 -40 to 85 pg-dso-20 industrial saf-xc824mt-1fgi flash 4 -40 to 85 pg-dso-20 industrial sax-xc824m-1fgi flash 4 -40 to 105 pg-dso-20 industrial sak-xc824m-1fgi flash 4 -40 to 125 pg-dso-20 industrial saf-xc822-1fra flash 4 -40 to 85 pg-tssop-16 automotive saf-xc822mt-1fra flash 4 -40 to 85 pg-tssop-16 automotive sak-xc822-1fra flash 4 -40 to 1 25 pg-tssop-16 automotive sak-xc822mt-1fra flash 4 -40 to 125 pg-tssop-16 automotive
xc822/824 summary of features data sheet 4 v1.1, 2010-10 as this document refe rs to all the derivati ves, some descripti on may not apply to a specific product. for simplicity, all versions are referred to by the term xc822/824 throughout this document. ordering information the ordering code for infi neon technologies microcontrollers provides an exact reference to the requ ired product. this or dering code identifies: ? the derivative itself, i.e. its function se t, the temperature range, and the supply voltage ? the package and the type of delivery for the available orderi ng codes for the xc82 2/824, please refer to your responsible sales representative or your local distributor.
xc822/824 general device information data sheet 5 v1.1, 2010-10 2 general device information chapter 2 contains the block diagram, pin configur ations, definitions an d functions of the xc822/824. 2.1 block diagram the block diagram of the xc822/824 is shown in figure 2 . figure 2 xc822/824 block diagram adc port 0 port 1 port 2 mdu ssc rtc 8-kbyte boot rom 1) 256-byte ram + 64-byte monitor ram 256-byte xram 2/4-kbyte flash xc800 core t0 & t1 uart 1) includes 1-kbyte monitor rom p0.0 - p0.6 p1.0 - p1.5 p2.0 ? p2.3 clock generator 48 mhz on-chip osc internal bus v ddp v ssp v ssc xc822/824 timer 2 ccu6 wdt ocds iic led and touch sense controller scu evr 75 khz on-chip osc
xc822/824 general device information data sheet 6 v1.1, 2010-10 2.2 logic symbol the logic symbol of the xc822/824 is shown in figure 3 . figure 3 xc822/8 24 logic symbol xc824 v ddp v ssp v ddc port 0 7-bit port 1 6-bit port 2 4-bit xc822 v ddp v ssp v ddc port 0 7-bit port 1 2-bit port 2 4-bit
xc822/824 general device information data sheet 7 v1.1, 2010-10 2.3 pin configuration the pin configuration of the xc822 in figure 4 . figure 4 xc822 pin configurat ion, pg-tssop-16 package (top view) p1.0/spd_1/rxd_2/t2ex_2/exint0_2/ col0_0/cout60_0/txd_1 p0.6/spd_0/rxd_1/sda_0/mtsr_1/mrst_0/ exint0_1/t2ex_0/line6/tsin6/txd_0/ col2_1/cola_1 p0.5/rxd_0/rtcclk/mtsr_0/mrst_1/ exint0_0/line5/tsin5/cout62_1/txd_3/ col1_1/exf2_2 p0.1/t0_0/cc61_1/mtsr_3/mrst_2/ t13hr_0/ccpos1_0/line1/tsin1 p0.2/t1_0/cc62_1/scl_1/ccpos2_0/ line2/tsin2 p0.0/t2_0/t13hr_1/mtsr_2/ mrst_3/t12hr_0/ccpos0_0/line0/ tsin0/cout61_1 v ddp v ssp v ddc p2.1/ccpos1_1/rxd_3/mtsr_4/t0_1/ exint1_1/an1 p1.2/exint4/col2_0/cout61_0/ cout63_0 p2.2/ccpos2_1/t12hr_3/t13hr_3/ sck_1/t1_1/exint2/an2 p2.0/ccpos0_1/t12hr_2/t13hr_2/t2ex_3/ t2_1/exint0_3/an0 p2.3/ccpos0_2/ctrap_2/t2_2/exint3/an3 1 2 3 4 5 6 7 8 15 14 13 12 11 10 9 16 xc822 p0.3/cc60_1/sda_1/ctrap_0/ line3/tsin3 p0.4/t2ex_1/scl_0/sck_0/exint1_0/ ctrap_1/line4/tsin4/exf2_0/col0_1/ col3_1/cola_2
xc822/824 general device information data sheet 8 v1.1, 2010-10 the pin configuration of the xc824 in figure 5 . figure 5 xc824 pin configurat ion, pg-dso-20 package (top view) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 17 xc824 9 10 18 19 20 p1.0/spd_1/rxd_2/t2ex_2/exint0_2/ col0_0/cout60_0/txd_1 p1.4/exint5/col4/cout62_0/ cout63_1 p0.6/spd_0/rxd_1/sda_0/mtsr_1/ mrst_0/exint0_1/t2ex_0/line6/tsin6/ txd_0/col2_1/cola_1 p1.5/cc62_0/col5/cola_0 p2.1/ccpos1_1/rxd_3/mtsr_4/t0_1/ exint1_1/an1 p1.2/exint4/col2_0/cout61_0/ cout63_0 p2.2/ccpos2_1/t12hr_3/t13hr_3/ sck_1/t1_1/exint2/an2 p1.1/cc60_0/col1_0/txd_2 p2.0/ccpos0_1/t12hr_2/t13hr_2/ t2ex_3/t2_1/exint0_3/an0 p2.3/ccpos0_2/ctrap_2/t2_2/ exint3/an3 p0.5/rxd_0/rtcclk/mtsr_0/mrst_1/ exint0_0/line5/tsin5/cout62_1/txd_3/ col1_1/exf2_2 p1.3/cc61_0/col3_0/cc61_0/exf2_1 p0.1/t0_0/cc61_1/mtsr_3/mrst_2/ t13hr_0/ccpos1_0/line1/tsin1 p0.2/t1_0/cc62_1/scl_1/ccpos2_0/ line2/tsin2 p0.0/t2_0/t13hr_1/mtsr_2/mrst_3/ t12hr_0/ccpos0_0/line0/tsin0/cout61_1 v ddp v ssp v ddc p0.3/cc60_1/sda_1/ctrap_0/ line3/tsin3 p0.4/t2ex_1/scl_0/sck_0/exint1_0/ ctrap_1/line4/tsin4/exf2_0/col0_1/ col3_1/cola_2
xc822/824 general device information data sheet 9 v1.1, 2010-10 2.4 pin definitions and functions the functions and defa ult states of the xc 822/824 external pi ns are provided in table 3 . table 3 pin definitions and functions for xc822/824 symbol pin number dso20/ tssop16 type reset state function p0 i/o port 0 port 0 is a bidirectional general purpose i/o port. it can be used as alte rnate functions for ledtscu, timer 0, 1 and 2, ssc, ccu6, iic, spd and uart. p0.0 15/12 hi-z t2_0 timer 2 input t13hr_1 ccu6 timer 13 hardware run input mtsr_2 ssc master transmit output/ slave receive input mrst_3 ssc master receive input t12hr_0 ccu6 timer 12 hardware run input ccpos0_0 ccu6 hall input 0 tsin0 touch-sense input 0 line0 led line 0 cout61_1 output of capture/compare channel 1
xc822/824 general device information data sheet 10 v1.1, 2010-10 p0.1 16/13 hi-z t0_0 timer 0 input cc61_1 input/output of capture/compare channel 1 mtsr_3 ssc slave receive input mrst_2 ssc master receive input/ slave transmit output t13hr_0 ccu6 timer 13 hardware run input ccpos1_0 ccu6 hall input 1 tsin1 touch-sense input 1 line1 led line 1 p0.2 17/14 hi-z t1_0 timer 1 input cc62_1 input/output of capture/compare channel 2 scl_1 iic clock line ccpos2_0 ccu6 hall input 2 tsin2 touch-sense input 2 line2 led line 2 p0.3 18/15 hi-z cc60_1 input/o utput of capture/compare channel 0 sda_1 iic data line ctrap_0 ccu6 trap input tsin3 touch-sense input 3 line3 led line 3 table 3 pin definitions and functions for xc822/824 symbol pin number dso20/ tssop16 type reset state function
xc822/824 general device information data sheet 11 v1.1, 2010-10 p0.4 19/16 pd t2ex_1 timer 2 external trigger input sck_0 ssc clock input/output scl_0 iic clock line ctrap_1 ccu6 trap input exint1_0 external interrupt input 1 tsin4 touch-sense input 4 line4 led line 4 exf2_0 timer 2 overflow flag col0_1 led column 0 col3_1 led column 3 cola_2 led column a p0.5 20/1 hi-z rxd_0 uart receive input rtcclk rtc external clock input mtsr_0 ssc master transmit output/ slave receive input mrst_1 ssc master receive input exint0_0 external interrupt input 0 tsin5 touch-sense input 5 line5 led line 5 cout62_1 output of capture/compare channel 2 txd_3 uart transmit output/ 2-wire uart bsl transmit output col1_1 led column 1 exf2_2 timer 2 overflow flag table 3 pin definitions and functions for xc822/824 symbol pin number dso20/ tssop16 type reset state function
xc822/824 general device information data sheet 12 v1.1, 2010-10 p0.6 1/2 pu spd_0 spd input/output rxd_1 uart receive input/ uart bsl receive input sda_0 iic data line mtsr_1 ssc slave receive input mrst_0 ssc master receive input/ slave transmit output exint0_1 external interrupt input 0 t2ex_0 timer 2 exte rnal trigger input tsin6 touch-sense input 6 line6 led line 6 txd_0 uart transmit output/ 1-wire uart bsl transmit output col2_1 led column 2 cola_1 led column a p1 i/o port 1 port 1 is a bidirectional general purpose i/o port. it can be used as altern ate functions for ccu6, ledtscu, spd, uart and timer 2. p1.0 8/7 hi-z spd_1 spd input/output rxd_2 uart receive input t2ex_2 timer 2 exte rnal trigger input exint0_2 external interrupt input 0 col0_0 led column 0 cout60_0 output of capture/compare channel 0 txd_1 uart transmit output table 3 pin definitions and functions for xc822/824 symbol pin number dso20/ tssop16 type reset state function
xc822/824 general device information data sheet 13 v1.1, 2010-10 p1.1 9/- hi-z cc60_0 input/output of capture/compare channel 0 col1_0 led column 1 txd_2 uart transmit output p1.2 10/8 hi-z exint4 external interrupt input 4 col2_0 led column 2 cout61_0 output of capture/compare channel 1 cout63_0 output of capture/compare channel 3 p1.3 11/- hi-z cc61_0 input/out put of capture/compare channel 1 col3_0 led column 3 exf2_1 timer 2 overflow flag p1.4 2/- hi-z exint5 external interrupt input 5 col4 led column 4 cout62_0 output of capture/compare channel 2 cout63_1 output of capture/compare channel 3 p1.5 3/- hi-z cc62_0 input/output of capture/compare channel 2 col5 led column 5 cola_0 led column a p2 i port 2 port 2 is a general purpos e input-only port. it can be used as inputs for a/ d converter and out of range comparator, ccu6, timer 2, ssc and uart. table 3 pin definitions and functions for xc822/824 symbol pin number dso20/ tssop16 type reset state function
xc822/824 general device information data sheet 14 v1.1, 2010-10 p2.0 7/6 hi-z ccpos0_1 ccu6 hall input 0 t12hr_2 ccu6 timer 12 hardware run input t13hr_2 ccu6 timer 13 hardware run input t2ex_3 timer 2 exte rnal trigger input t2_1 timer 2 input exint0_3 external interrupt input 0 an0 analog input 0 / out of range comparator channel 0 p2.1 6/5 hi-z ccpos1_1 ccu6 hall input 1 rxd_3 uart receive input mtsr_4 slave receive input t0_1 timer 0 input exint1_1 external interrupt input 1 an1 analog input 1 / out of range comparator channel 1 p2.2 5/4 hi-z ccpos2_1 ccu6 hall input 2 t12hr_3 ccu6 timer 12 hardware run input t13hr_3 ccu6 timer 13 hardware run input sck_1 ssc clock input/output t1_1 timer 1 input exint2 external interrupt input 2 an2 analog input 2 / out of range comparator channel 2 table 3 pin definitions and functions for xc822/824 symbol pin number dso20/ tssop16 type reset state function
xc822/824 general device information data sheet 15 v1.1, 2010-10 2.5 memory organization the xc822/824 cpu operates in the following five address spaces: ? 8 kbytes of boot rom, li brary rom and user routines ? 256 bytes of internal ram ? 256 bytes of xram (xram can be read/written as program memory or external data memory) ? a 128-byte special function register area ? 2/4 kbytes of flash figure 6 illustrates the memory address spaces of the 2 kbyte flash devices. there are two 1-kbyte sectors in this device. figure 7 illustrates the memo ry address spaces of the 4 kbyte flash devic es. this device has two 1-kbyte sectors, two 512-byte sectors, two 256-byte sector s and four 128-byte sectors. figure 8 shows the flash sectorization for 2 kbyte and 4 kbyte flash devices. p2.3 4/3 hi-z ccpos0_2 ccu6 hall input 0 ctrap_2 ccu6 trap input t2_2 timer 2 input exint3 external interrupt input 3 an3 analog input 3 / out of range comparator channel 3 v ddp 12/9 ? i/o port supply (2.5 v - 5.5 v) v ddc 14/11 ? core supply output (2.5 v) v ssp / v ssc 13/10 ? i/o port ground/ core supply ground table 3 pin definitions and functions for xc822/824 symbol pin number dso20/ tssop16 type reset state function
xc822/824 general device information data sheet 16 v1.1, 2010-10 figure 6 memory map of xc822/824 with 2 kbytes of flash memory 0000 h 0800 h f000 h c000 h e000 h f100 h ffff h flash bank 0 2 kbytes boot rom 8 kbytes xram 256 bytes f000 h f100 h 0000 h ffff h special function registers indirect address direct address 80 h ff h 00 h code space external data space internal data space internal ram memory map user mode xram 256 bytes 7f h internal ram a800 h flash bank 0 2 kbytes 1) a000 h in debug mode, this 64-byte address area is replaced by a 64-byte monitor ram. 40 h 1) physically one 2-kbyte flash bank , mapped to both address range .
xc822/824 general device information data sheet 17 v1.1, 2010-10 figure 7 memory map of xc822/824 with 4 kbytes of flash memory 0000 h 1000 h f000 h c000 h e000 h f100 h ffff h flash bank 0 4 kbytes boot rom 8 kbytes xram 256 bytes f000 h f100 h 0000 h ffff h special function registers indirect address direct address 80 h ff h 00 h code space external data space internal data space internal ram memory map user mode xram 256 bytes 7f h internal ram b000 h flash bank 0 4 kbytes 1) a000 h in debug mode, this 64-byte address area is replaced by a 64-byte monitor ram. 40 h 1) physically one 4-kbyte flash bank , mapped to both address range .
xc822/824 general device information data sheet 18 v1.1, 2010-10 figure 8 flash bank sectorization 2.6 jtag id jtag id register is a read-o nly register located inside th e jtag module, and is used to recognize the dev ice(s) connected to the jtag interface. its cont ent is shifted out when instruction register contains the idcode comma nd (opcode 04 h ), and the same is also true immediately after reset. the jtag id register contents for th e xc822/824 flash devices are given in table 4 . note: the asterisk (*) ab ove denotes all possible device configurations. table 4 jtag id summary device type device name jtag id flash xc822/824* 101b c083 h sector 9: 128-byte sector 5: 256-byte sector 3: 512-byte sector 1: 1-kbyte 1) sector 0: 1-kbyte 1) sector 7: 128-byte sector 8: 128-byte sector 6: 128-byte sector 4: 256-byte sector 2: 512-byte 1x flash bank 1) 2 kbyte flash devices only has sector 0 and sector 1.
xc822/824 general device information data sheet 19 v1.1, 2010-10 2.7 chip identification number the xc822/824 identity (id) register is located at page 1 of address b3 h . the value of id register is 51 h . however, for easy identificati on of product variants, the chip identification number, which is an unique number assigned to each product variant, is available. the differentiatio n is based on the product a nd variant type information. two methods are prov ided to read a device?s ch ip identification number: ? in-application subr outine, get_chip_info ? boot-loader (bsl) mode a table 5 lists the chip identi fication numbers of xc 822/824 device variants. table 5 chip identification number product variant chip identification number xc822t-0fri 51080343 h xc822-1fri 51080163 h xc822t-1fri 51080143 h xc822m-1fri 51080123 h xc822mt-1fri 51080103 h xc824m-1fgi 51080122 h xc824mt-1fgi 51080102 h
xc822/824 electrical parameters data sheet 20 v1.1, 2010-10 3 electrical parameters chapter 3 provides the characteristics of th e electrical parameters which are implementation-specifi c for the xc822/824. 3.1 general parameters the general parameters are described here to aid the us ers in interpreting the parameters mainly in section 3.2 and section 3.3 . 3.1.1 parameter interpretation the parameters listed in this section represent part ly the characteristics of the xc822/824 and partly it s requirements on the system. to aid interpreting the parameters easily when evaluating them for a design, they ar e indicated by the abb reviations in the ?symbol? column: ? cc ? these parameters indicate c ontroller c haracteristics, which are distinctive features of the xc822/824 and must be regarded for a system design. ? sr ? these paramete rs indicate s ystem r equirements, which must be provided by the microcontroller system in whic h the xc822/824 is designed in.
xc822/824 electrical parameters data sheet 21 v1.1, 2010-10 3.1.2 absolute maximum rating maximum ratings are the extreme limits to which the xc822/8 24 can be subjected to without permanent damage. note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditio ns above thos e indicated in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum ra ting overload conditions ( v in > v ddp or v in < v ss ) the voltage on v ddp pin with respect to ground ( v ss ) must not exceed the values defined by the absol ute maximum ratings. table 6 absolute maximu m rating parameters parameter symbol limit values unit notes min. max. ambient temperature t a -40 125 c under bias storage temperature t st -65 150 c? junction temperature t j -40 150 c under bias voltage on power supply pin with respect to v ss v ddp -0.5 6 v input current on any pin during overload condition i in -10 10 ma absolute sum of all input currents during overload condition | i in |? 50 ma
xc822/824 electrical parameters data sheet 22 v1.1, 2010-10 3.1.3 operating condition the following operating conditions must not be exceed ed in order to ensure correct operation of the xc822/824. all parameters menti oned in the following tables refer to these operating co nditions, unless otherwise noted. table 7 operating condition parameters parameter symbol limit values unit notes/ conditions min. max. digital power supply voltage v ddp 3.0 5.5 v 2.5 3.0 v 1) 1) in this voltage range, limited operations are available in active mode. operations in power save modes are fully supported. cpu clock frequency f cclk 22.5 25.6 mhz typ. 24 mhz 7.5 8.5 mhz typ. 8 mhz ambient temperature t a -40 85 c saf-xc822/824... -40 105 c sax-xc824... -40 125 c sak-xc824...
xc822/824 electrical parameters data sheet 23 v1.1, 2010-10 3.2 dc parameters the electrical characteristic s of the dc parameters are detailed in this section. 3.2.1 input/output characteristics table 8 provides the characteri stics of the input/output pins of the xc822/xc824. table 8 input/output characteristics of xc822/xc824 (operating conditions apply) parameter symbol limit valu es unit test conditions min. max. output low voltage on port pins v olp cc ? 1.0 v i ol = 25 ma (5 v) i ol = 13 ma (3.3 v) ?0.4v i ol = 10 ma (5 v) i ol =5ma (3.3v) output high voltage on port pins v ohp cc v ddp - 1.0 ?v i oh =-15ma (5v) i oh = -8 ma (3.3 v ) v ddp - 0.4 ?v i oh = -5 ma (5 v) i oh = -2.5 ma (3.3 v) input low voltage on port pins v ilp sr ? 0.3 v ddp v cmos mode input high voltage on port pins v ihp sr 0.7 v ddp ?vcmos mode input hysteresis 1) hys cc 0.08 v ddp ?vcmos mode (5v) 0.03 v ddp ? v cmos mode (3.3 v) 0.01 v ddp ? v cmos mode (2.5 v) pull-up current on port pins i pup cc ? -20 a v ih,min (5 v) -150 ? a v il,max (5 v) ?-5 a v ih,min (3.3 v) -100 ? a v il,max (3.3 v)
xc822/824 electrical parameters data sheet 24 v1.1, 2010-10 pull-down current on port pins i pdp cc ? 20 a v il,max (5 v) 150 ? a v ih,min (5 v) ?5 a v il,max (3.3 v) 100 ? a v ih,min (3.3 v) input leakage current on port pins 2) i ozp cc -1 1 a0 < v in < v ddp , t a 125 c overload current on any pin i ovp sr -5 5 ma 3) absolute sum of overload currents | i ov |sr? 25 ma 3) voltage on any pin during v ddp power off v po sr ? 0.3 v 4) maximum current per pin (excluding v ddp and v ss ) i m sr -15 25 ma ? maximum current into v ddp i mvddp sr ? 80 ma 3) maximum current out of v ss i mvss sr ? 80 ma 3) 1) not subjected to production test, verified by design/characterization. hysteresis is implemented to avoid meta stable states and switching due to internal ground bounc e. it cannot be guaranteed that it suppresses switching due to external system noise. 2) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. 3) not subjected to production test, verified by design/characterization. 4) not subjected to production test, verified by design/char acterization. however, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any gpio pin when v ddp is powered off. table 8 input/output characteristics of xc822/xc824 (operating conditions apply) (cont?d) parameter symbol limit valu es unit test conditions min. max.
xc822/824 electrical parameters data sheet 25 v1.1, 2010-10 3.2.2 supply threshold characteristics table 9 provides the characteri stics of the supply thre shold in the xc822/824. figure 9 supply threshold parameters table 9 supply threshold paramete rs (operating conditions apply) parameters symbol limit values unit min. typ. max. v ddp prewarning voltage 1)2) 1) detection is enabled via sdcon register in active mode. it is automatically disabled in power down mode. detection should be disabled for v ddp less than maximum of v ddppw . 2) this parameter has a hysteresis of 50 mv. v ddppw cc 3.0 3.6 4.5 v v ddp brownout voltage in active mode 3)2) 3) detection is enabled via sdcon register. dete ction must be disabled for application with v ddp less than the specified values. v ddpboa cc 2.65 2.75 2.87 v v ddp brownout voltage in power down mode 2)3) v ddpbopd cc 3.0 3.6 4.5 v v ddp system reset release voltage 2)4) 4) v ddpsrr and v ddcsrr must be met before the system reset is released. v ddpsrr cc 2.7 2.8 2.92 v v ddc prewarning voltage 2)5) 5) detection is enabled via sdcon register in active mode. it is automatically disabled in power down mode. v ddcpw cc 2.3 2.4 2.48 v v ddc brownout voltage in active mode 2) v ddcboa cc 2.25 2.3 2.42 v v ddc brownout voltage in power down mode 2) v ddcbopd cc 1.35 1.5 1.95 v v ddc system reset release voltage 2)4) v ddcsrr cc 2.28 2.3 2.47 v ram data retention voltage v ddcrdr cc 1.1 ? ? v vddp vddc v ddppw /v ddpbopd v ddcsrr v ddcpw v ddcboa v ddcrdr 5.0v 2.5v v ddcbopd v ddpboa v ddpsrr
xc822/824 electrical parameters data sheet 26 v1.1, 2010-10 3.2.3 adc characteristics the values in table 10 are given for an analog power supply of 5.0 v . the adc can be used with an analog po wer supply down to 3 v . but in this case, analog parameters may show a reduced performances. in the reduced vo ltage mode (2.5 v < v ddp < 3 v), the adc is not recommend ed to be used. table 10 adc characteristics (o perating conditions apply; v ddp = 5 v) parameter symbol limit valu es unit test conditions / remarks min. typ. max. analog reference voltage v aref ? v ddp ? v connect internally to v ddp analog reference ground v agnd ? v ssp ? v connect internally to v ssp alternate analog reference ground v agndalt sr v ssp - 0.1 ?2.5 1) v connect to an0 in differential mode, see figure 10 . internal voltage reference v intref sr 1.19 1.23 1.28 v 3) analog input voltage range v ain sr v agnd ? v aref v? adc clock f adci 8 ? 16 mhz internal analog clock sample time t s cc (2 + inpcr0.stc) t adci s? conversion time t c cc see section 3.2.3.1 s? total unadjusted error tue 2) cc ? ? 1 lsb8 8-bit conversion with internal reference 3) ? ? +4/-1 lsb10 10-bit conversion with internal reference 3)4) ? ? +14/-2 lsb12 12-bit conversion using the low pass filter 3) differential nonlinearity ea dnl cc ? ? +1.5/ -1 lsb 10-bit conversion 3)
xc822/824 electrical parameters data sheet 27 v1.1, 2010-10 integral nonlinearity ea inl cc ? ? 1.5 lsb 10-bit conversion 3) offset ea off cc ? +4 ? lsb 10-bit conversion 3) gain ea gain cc ? -4 ? lsb 10-bit conversion 3) switched capacitance at an analog input c ainsw cc ? 2 3 pf 3)5) total capacitance at an analog input c aint cc ? ? 12 pf 3)5) input resistance of an analog input r ain cc ? 1.5 2 k ? 3) 1) 1.2 v at v ddp =3.0v. 2) tue is tested at v aref = v ddp = 5.0 v and cpu clock ( f sclk, cclk )=8mhz. 3) not subject to production test, verified by design/characterization. 4) if a reduced positive reference voltage is used, tue w ill increase. if the positive reference is reduced by a factor of k, the tue will increased by 1/k. example:k = 0.8, 1/k = 1.25; 1.25 x tue = 2.5 lsb10. 5) the sampling capacity of the conversion c-network is pre-charged to v aref /2 before connecting the input to the c-network. because of the parasitic element s, the voltage measured at anx is lower than v aref /2. table 10 adc characteristics (o perating conditions apply; v ddp = 5 v) parameter symbol limit valu es unit test conditions / remarks min. typ. max.
xc822/824 electrical parameters data sheet 28 v1.1, 2010-10 figure 10 differential like me asurement with internal 1.2v voltage reference, and ch0 gnd. figure 11 adc input circuits ad converter conversion control request control interrupt generation adc kernel result handling v 1.2vref v 1.2vgnd va_altgnd va_altref ain ch0 ain ch1 ain ch3 ... v ssp r ext analog input circuitry v ain c ext anx c ainsw r ain, on c aint -c ainsw
xc822/824 electrical parameters data sheet 29 v1.1, 2010-10 3.2.3.1 adc conversion timing conversion time, t c = t adc (1 + r (3+n+stc)), where ? r=ctc+3, ? ctc = conversion time control (globctr.ctc), ? stc = sample time control (inpcr0.stc), ? n = 8 or 10 (for 8-bit and 10-bit conversion respectively), ? t adc =1/ f adc 3.2.3.2 out of range comparator characteristics table 11 below shows the out of rang e comparator characteristics. table 11 out of range comparator ch aracteristics (operating conditions apply) parameter symbol limit values unit remarks min. typ. max. dc switching level v sensedc sr 60 125 270 mv above v ddp dc hysteresis v sensehys cc 30 ? ? mv 1) 1) not subject to production test, verified by design/characterization. pulse width t sensepw sr 300 ? ? ns anx > v ddp 1) switching delay t sensesd cc ? ? 400 ns anx >= v ddp +350mv 1) pulse switching level t sensepsl sr ? 250 ? mv @ 300 nsec 1) sr ? 60 ? mv @ 800 usec 1)
xc822/824 electrical parameters data sheet 30 v1.1, 2010-10 3.2.4 flash memory parameters the xc822/824 is delivered with all flash sectors erased (read all zeros). the data retention time of the xc822/824?s flas h memory (i.e. the time after which stored data can still be retrie ved) depends on the number of times the flash memory has been erased and programmed. note: flash memory parameters are not subject to production test bu t verified by design and/or characterization. table 12 flash timing parameters (operating conditions apply) parameter symbol limit values unit remarks min. typ. max. read access time (per byte) t acc cc ? 125 ? ns programming time (per wordline) t pr cc ? 2.2 ? ms erase time (one or more sectors) t er cc ? 120 ? ms flash wait states n wsflash cc 0 cpu clock = 8 mhz 1cpu clock=24mhz table 13 flash data retent ion and endurance (opera ting conditions apply) retention endurance 1) 1) one cycle refers to the pr ogramming of all wordlines in a sector and erasing of sector. the flash endurance data specified in table 13 is valid only if the following conditions are fulfilled: - the maximum number of erase cycles per flas h sector must not e xceed 100,000 cycles. - the maximum number of erase cycles per flash bank must not exceed 300,000 cycles. - the maximum number of program cycles per flash bank must not exceed 2,500,000 cycles. size remarks 20 years 1,000 cycl es up to 8 kbytes 5 years 10,000 cycles 1 kbyte 2 years 70,000 cycles 512 bytes 2 years 100,000 cycles 128 bytes
xc822/824 electrical parameters data sheet 31 v1.1, 2010-10 table 14 emulated flash data retent ion and endurance based on eeprom emulation rom library (ope rating conditions apply) 1) 1) eeprom emulation rom library can only be used in the 4 kbyte flash variant. retention endurance 2) 2) these values show the maximum endurance. maximum endurance is the maximum possible unique data write if each data update is only 31 bytes. minimum endur ance cycle is the maximum possible unique data write if each data update is the same as the emulation size. the minimum endurance cycle can be calculated using the formulae [(max. endurance)*(31)/(emulation size)]. emulation size remarks 2 years 1,600,000 cycles 31 bytes 2 years 1,400,000 cycles 62 bytes 2 years 1,200,000 cycles 93 bytes 2 years 1,000,000 cycles 124 bytes
xc822/824 electrical parameters data sheet 32 v1.1, 2010-10 3.2.5 power supply current table 15 provides the characteri stics of the power supply current in the xc822/824. table 15 power cons umption parameters 1) 2) (operating conditions apply) 1) the typical values are measured at t a =+25 c and v ddp = 5 v and 3.3 v. 2) the maximum values are measured under worst case conditions ( t a =+125 c and v ddc =5v). parameter symbol limit va lues unit test condition typ. max. active mode i ddpa 21 25 ma 5 v / 3.3 v 3) 3) i ddpa (active mode) is measured with: cpu clock and input clock to all peripherals running at 24 mhz (clkmode=0). 14 18 ma 5 v / 3.3 v 4) 4) i ddpa (active mode) is measured with: cpu clock and input clock to all peripherals running at 8 mhz (clkmode=1). ?5 ma2.5v 5) 5) this value is based on the maximum load capacity of evr during v ddp = 2.5 v. not subject to production test, verified by design/characterisation. idle mode i ddpi 16 20 ma 5 v / 3.3 v 6) 6) i ddpi (idle mode) is measured with: cpu clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 mhz (clkmode=0). ?5 ma2.5v 5) power down mode 1 i pdp1 35 a t a = 25 c 7) 7) i pdp1 and i pdp2 is measured at 5 v and 3.3 v with: wake-up port is programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. ?28 a t a = 85 c 7)8)9) 8) not subject to production test, verified by design/characterisation. 9) i pdp1 and i pdp2 has a maximum values of 100 ua at t a = + 125 c. power down mode 2 i pdp2 57 a t a = 25 c 7) ?30 a t a = 85 c 7)8)
xc822/824 electrical parameters data sheet 33 v1.1, 2010-10 table 16 shows the maximum active current with in the device in the reduced voltage condition of 2.5 v < v ddp < 3.0 v. the active current cons umption needs to be below the specified values as according to the v ddp voltage. if the conditions are not met, a brownout reset may be triggered. table 17 provides the active current consumpt ion of some module s operating at 8 mhz active mode, 3 v power supply at 25 c. the typical values shown are used as a reference guide for device operatin g in reduced volt age conditions. table 16 active current consumpti on in reduced volt age condition v ddp 2.5v 2.6v 2.7v 2.8v maximum active current 7ma 13ma 20ma 25ma table 17 typical active current consumption 1) 2) 1) modules that are controllable by programming the register pmcon1. 2) not subject to production test, verified by design/characterisation. active current consumption symbol limit values unit test condition typ. baseload current 3) 3) baseload current is measured when the device is running in user mode with an endless loop in the flash memory. all modules in register pmcon1 are disabled. i cpuddc 5850 a modules including core, memories, uart, t0, t1 and evr. disable adc analog (globctr.anon = 0). adc 4) 4) adc active current is measured with: module enable, adc analog clock at 8mhz, running in parallel conversion request in autoscan mode for 4 channels i adcddc 3390 a set pmcon1.adc_dis to 0 and globectr. anon to 1 ssc 5) 5) ssc active curremt is measured with: module enabled, running in loop back mode at a baud rate of 1 mbaud i sscddc 460 a set pmcon1.ssc_dis to 0 ccu6 6) 6) ccu6 active current is measured with: module enabled, all timers running in 8 mhz, 6 pwm outputs are generated. i ccu6ddc 3320 a set pmcon1.ccu_dis to 0 timer 2 7) 7) timer 2 active current is measured with: module enabled, timer running in 8 mhz i t2ddc 200 a set pmcon1.t2_dis to 0 mdu 8) 8) mdu active current is measured with: module enabled, division operation was performed. i mduddc 1260 a set pmcon1.mdu_dis to 0 ledtscu 9) i ledddc 520 a set pmcon1.lts_dis to 0 iic 10) i iicddc 580 a set pmcon1.iic_dis to 0
xc822/824 electrical parameters data sheet 34 v1.1, 2010-10 9) ledtscu active curent is measured with : module enabled, counter running in 8 mhz. 10) iic active current is measured with: module enabled , performing a master transmit with the master clock running at 400 khz.
xc822/824 electrical parameters data sheet 35 v1.1, 2010-10 3.3 ac parameters the electrical characteristic s of the ac parameters are detailed in this section. 3.3.1 testing waveforms the testing waveforms for ri se/fall time, output delay and output high impedance are shown in figure 12 , figure 13 and figure 14 . figure 12 rise/fall time parameters figure 13 testing waveform, output delay figure 14 testing waveform , output high impedance 10% 90% 10% 90% v ss v ddp t r t f v dde / 2 test points v dde / 2 v ss v ddp v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v
xc822/824 electrical parameters data sheet 36 v1.1, 2010-10 3.3.2 output rise/fall times table 18 provides the characterist ics of the output rise/fall times in the xc822/824. figure 15 rise/fall times parameters table 18 output rise/fall times para meters (operating conditions apply) parameter symbol limit valu es unit test conditions min. max. rise/fall times on standard pad 1)2) 1) rise/fall time parameters are taken with 10% - 90% of supply. 2) not all parameters are 100% tested, but are verified by design/characterisation and test correlation. t r , t f ?10ns20 pf 3)4) (5 v & 3.3 v). 3) additional rise/fall time valid for c l =20pf-c l = 100 pf @ 0.125 ns/pf at 5 v supply voltage. 4) additional rise/fall time valid for c l =20pf-c l = 100 pf.@ 0.225 ns/pf at 3.3 v supply voltage. t r 10% 90% 10% 90% t f v ss v ddc
xc822/824 electrical parameters data sheet 37 v1.1, 2010-10 3.3.3 oscillator timing and wake-up timing table 19 provides the characteri stics of the powe r-on reset, pll and wake-up timings in the xc822/824. 3.3.4 on-chip oscillator characteristics table 20 provides the characteristics of th e 48 mhz oscillator in the xc822/824. table 19 power-on reset wake-up timing 1) (operating conditions apply) 1) not subject to production test, verified by design/characterisation. parameter symbol limit va lues unit test conditions min. typ. max. 48 mhz oscillator start-up time t 48moscst cc ? ? 13 s 75 khz oscillator start- up time t 75koscst cc ? ? 800 s flash initialization time t fint cc ? 160 ? s table 20 48 mhz oscillator characteri stics (operating conditions apply) parameter symbol limit valu es unit test conditions min. typ. max. nominal frequency f nom cc -0.5 % 48 +0.5% mhz under nominal conditions 1) after trimming 1) nominal condition: v ddc =2.5v, t a =+25 c. long term frequency deviation ? f lt cc -2.0 ? 3.0 % with respect to f nom , over lifetime and temperature (0 c to 85 c) -4.5 ? 4.5 % with respect to f nom , over lifetime and temperature (-40 c to 125 c) short term frequency deviation (over core supply voltage 2) ) 2) core voltage supply, v ddc = 2.5 v 7.5%. ? f st cc -1 ? 1 % with respect to f nom , within one lin message (< 10 ms ? 100 ms)
xc822/824 electrical parameters data sheet 38 v1.1, 2010-10 table 21 provides the characteristics of th e 75 khz oscillator in the xc822/824. table 21 75 khz oscillator characteri stics (operating conditions apply) parameter symbol limit values unit test conditions min. typ. max. nominal frequency f nom cc -1% 75 +1% khz under nominal conditions 1) after trimming 1) nominal condition: v ddc =2.5v, t a =+25 c. long term frequency deviation ? f lt cc -4.5 ? 4.5 % with respect to f nom , over lifetime and temperature (-40 c to 125 c) short term frequency deviation ? f st cc -1.5 ? 1.5 % with respect to f nom , over core supply voltage of 2.5 v 7.5%
xc822/824 electrical parameters data sheet 39 v1.1, 2010-10 3.3.5 ssc timing 3.3.5.1 ssc master mode timing table 22 provides the ssc master m ode timing in the xc822/824. figure 16 ssc master mode timing table 22 ssc master mode timing 1) (operating conditions apply; cl = 50 pf) 1) not subject to production test, verified by design/characterisation. parameter symbol limit values unit min. max. sclk clock period t 0 cc 2 * t ssc 2) 2) t sscmin =t cpu =1/ f cpu . when f cpu = 24 mhz, t 0 = 83.3 ns. t cpu is the cpu clock period. ?ns mtsr delay from sclk t 1 cc 0 6 ns mrst setup to sclk t 2 sr 20 ? ns mrst hold from sclk t 3 sr 0 ? ns ssc_tmg1 sclk 1) mtsr 1) t 1 t 1 mrst 1) t 3 data valid t 2 t 1 1) this timing is based on the following setup: con.ph = con.po = 0. t 0
xc822/824 electrical parameters data sheet 40 v1.1, 2010-10 3.3.5.2 ssc slave mode timing table 23 provides the ssc slave mo de timing in the xc822/824. figure 17 ssc slave mode timing table 23 ssc slave mode timing 1) (operating conditio ns apply; cl = 50 pf) 1) not subject to production test, verified by design/characterisation. parameter symbol limit values unit min. max. sclk clock period t 0 sr 4 * t ssc 2) 2) t sscmin =t cpu =1/ f cpu . when f cpu = 24 mhz, t 0 = 166.7 ns. t cpu is the cpu clock period. ?ns mrst delay from sclk t 1 cc 0 20 ns mtsr setup to sclk t 2 sr 46 ? ns mtsr hold from sclk t 3 sr 0 ? ns t 2 t 3 t 1 sclk 1) mtsr 1) mrst 1) t 0 data valid 1) this timing is based on the following setup : con.ph = con.po = 0.
xc822/824 electrical parameters data sheet 41 v1.1, 2010-10 3.3.6 spd timing the spd interface will work with standard spd tools havi ng a sample/output clock fre- quency deviation of +/- 5% or less. for further detail s please refer to application note ap24004 in section spd timing requirements. note: these parameters are no subject to pr oduct test but verifi ed by design and/or characterization. note: operating conditions apply.
xc822/824 package and quality declaration data sheet 42 v1.1, 2010-10 4 package and quality declaration chapter 4 provides the informatio n of the xc822/824 packa ge and reliability section. 4.1 package parameters table 24 provides the thermal characteristic s of the packages used in xc822 and xc824 respectively. table 24 thermal characte ristics of the packages parameter symbol limit va lues unit package types min. max. thermal resistan ce junction case 1) 1) the thermal resistances between the case and the ambient ( r tca ) , the lead and the ambient ( r tla ) are to be combined with the thermal resistances between the junction and the case ( r tjc ), the junction and the lead ( r tjl ) given above, in order to calculate the total t hermal resistance between the junction and the ambient ( r tja ). the thermal resistances between the case and the ambient ( r tca ), the lead and the ambient ( r tla ) depend on the external system (pcb, case) characte ristics, and are under user responsibility. the junction temperature can be calculated using the following equation: t j = t a + r tja p d , where the r tja is the total thermal resistance between the junction and t he ambient. this total junction ambient resistance r tja can be obtained from the upper four partial thermal resistances, by a) simply adding only the two thermal resistances (junction lead and lead ambient), or b) by taking all four resistances into account, depending on the precision needed. r tjc cc - 36.2 k/w pg-tssop-16-1 - 34.3 k/w pg-dso-20-45 thermal resistan ce junction lead 1) r tjl cc - 356.6 k/w pg-tssop-16-1 - 36.2 k/w pg-dso-20-45
xc822/824 package and quality declaration data sheet 43 v1.1, 2010-10 4.2 package outline figure 18 and figure 19 shows the package outlines of the xc822 (tssop-16) and xc824 (dso-20) devices respectively. figure 18 pg-tssop-16-1 package outline
xc822/824 package and quality declaration data sheet 44 v1.1, 2010-10 figure 19 pg-dso-20-45 package outline
xc822/824 package and quality declaration data sheet 45 v1.1, 2010-10 4.3 quality declaration table 25 shows the characteristics of the quality parameters in the xc822/824. table 25 quality parameters parameter symbol limit values unit notes min. max. operation lifetime when the device is used at the three stated t j 1) 1) this lifetime refers only to the time when device is powered-on. t op1 - 1500 hours t j =150 c - 15000 hours t j =110 c - 1500 hours t j =-40 c operation lifetime when the device is used at the stated t j 1) t op2 - 131400 hours t j =27 c esd susceptibility according to human body model (hbm) v hbm - 2000 v conforming to eia/jesd22- a114-b esd susceptibility according to charged device model (cdm) pins v cdm - 500 v conforming to jesd22-c101-c
www.infineon.com published by infineon technologies ag

▲Up To Search▲

Price & Availability of SAF-XC822-1FRI

	To Download SAF-XC822-1FRI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .